4 Commits

Author	SHA1	Message	Date
tangxifan	2c7d6e3de4	adding port parsers	2019-08-09 17:48:55 -06:00
tangxifan	ad8c33e1ba	complete the mutators	2019-08-08 11:33:11 -06:00
tangxifan	38962c4607	adding member functions for circuit library	2019-08-07 15:45:27 -06:00
tangxifan	44d21ebb90	fixed a bug in Verilog generator supporting SRAM5T	2019-06-13 14:42:39 -06:00