4 Commits

Author	SHA1	Message	Date
AurelienUoU	a2f6ded2a2	Add path modification in file changing a keyword into OpenFPGA full path	2019-06-04 15:21:15 -06:00
AurelienUoU	17ad905b14	Update flow and allow netlist generation	2019-05-17 17:00:38 -06:00
AurelienUoU	f31339bb5c	Correctly instantiate script variables	2019-05-16 14:30:16 -06:00
AurelienUoU	c4ccff4562	Move Verilog test in another script to avoid false failure	2019-05-16 09:05:30 -06:00