Commit Graph

22 Commits

Author SHA1 Message Date
tangxifan 1d766d2a70 minor format fix on documentation 2020-03-11 10:22:30 -06:00
tangxifan 0da6f00af5 start reworking the openfpga tool documentation 2020-03-10 17:29:35 -06:00
tangxifan 751735bf41 update documentation in simulation setting syntax 2020-03-09 17:40:33 -06:00
BaudouinChauviere 01371ce54d
Update customize_subckt.rst 2019-04-01 16:27:06 -06:00
BaudouinChauviere 1ea7ec3265
Update spice_simulation.rst 2019-04-01 16:26:02 -06:00
BaudouinChauviere cfdc072164
Update file_organization.rst 2019-04-01 16:25:09 -06:00
BaudouinChauviere fcc3bf0967
Update command_line_usage.rst 2019-04-01 16:23:24 -06:00
BaudouinChauviere cd301a5bb8
Update file_organization.rst
Correction of the hierarchy
2018-12-03 14:09:11 -07:00
BaudouinChauviere 9c97125b0d
Update spice_simulation.rst
typo
2018-12-03 13:42:45 -07:00
BaudouinChauviere b8f702e16d
Update file_organization.rst
Creation of the table for better understanding
2018-12-03 13:40:42 -07:00
Aurelien Alacchi 4a950c6857 Flatten_hierarchy_doc 2018-10-18 16:28:12 -06:00
Aurelien Alacchi aa5449c37d Verif_modif_doc_title_2 2018-10-17 16:49:55 -06:00
Aurelien Alacchi 6327a4486b Revert "Verif_modif_doc_title"
This reverts commit 8f7f88ebea.
2018-10-17 16:47:32 -06:00
Aurelien Alacchi 8f7f88ebea Verif_modif_doc_title 2018-10-17 16:45:42 -06:00
Aurelien Alacchi 2cfbe2b997 FPGA-Verilog_doc_update 2018-10-17 16:38:03 -06:00
Aurelien Alacchi e96c6e2f02 Revert "Bug_correction_fpga-spice_commandLine"
This reverts commit 33e76d0255.
2018-10-12 16:09:14 -06:00
Aurelien Alacchi 33e76d0255 Bug_correction_fpga-spice_commandLine 2018-10-12 16:05:53 -06:00
Aurelien Alacchi 26538cb2bc Correction_file_commandline_fpga-spice 2018-10-12 16:03:23 -06:00
Aurelien Alacchi e0c2fc2c8a Documentation_code&example_update 2018-10-12 15:50:09 -06:00
唐希凡 0bfbc9b0aa update docs 2018-09-14 13:11:51 -06:00
Xifan Tang fec0daa2a8 Update a draft 2018-09-13 22:58:54 -06:00
Xifan Tang d6d6951496 Adding documentation 2018-09-13 15:38:41 -06:00