tangxifan
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6d31b319a2
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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tangxifan
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25f6c529e0
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[engine] fixed syntax errors when using clang
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2022-08-25 09:58:43 -07:00 |
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tangxifan
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e0ae851e28
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[engine] correcting compilation errors due to vpr upgrade
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2022-08-17 16:25:12 -07:00 |
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tangxifan
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36a4da863c
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[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
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2021-09-20 16:05:36 -07:00 |
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tangxifan
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6a0f4f354f
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[Tool] Support superLUT circuit model in core engine
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2021-02-09 20:23:05 -07:00 |
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tangxifan
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8ac6e10727
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bug fix in lut and mux module generation on supporting spypads
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2020-04-22 14:41:16 -06:00 |
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tangxifan
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2c0c5a061b
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spot a bug in assigning rr_switch in tileable routing
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2020-03-20 16:53:43 -06:00 |
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tangxifan
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c78d3e9af1
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add mux library builder
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2020-02-12 14:58:23 -07:00 |
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tangxifan
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4367dba9b7
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move mux graph and decoder builders to vpr8 integration; ready to link the rr_switch to circuit models
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2020-02-11 21:02:58 -07:00 |