5 Commits

Author	SHA1	Message	Date
tangxifan	5e36aa82c5	fixa bug in determining mux structure	2019-01-22 13:54:50 -07:00
tangxifan	e223868df8	fix bugs for wired LUTs	2018-11-27 12:46:30 -07:00
Aur??Lien ALACCHI	de2bc18bbb	bugs fixed for shift register benchmark	2018-11-26 16:58:45 -07:00
tangxifan	861c449606	support wired LUT in FPGA-SPICE and FPGA-Verilog	2018-11-15 15:57:49 -07:00
tangxifan	d683134b12	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00