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OpenFPGA
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344 Commits 72 Branches 8 Tags 105 MiB
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3 Commits

Author SHA1 Message Date
AurelienUoU 17ad905b14 Update flow and allow netlist generation 2019-05-17 17:00:38 -06:00
AurelienUoU f31339bb5c Correctly instantiate script variables 2019-05-16 14:30:16 -06:00
AurelienUoU c4ccff4562 Move Verilog test in another script to avoid false failure 2019-05-16 09:05:30 -06:00