4 Commits

Author	SHA1	Message	Date
tangxifan	ad06e9c98c	plug in module manager	2019-08-23 20:23:41 -06:00
tangxifan	931b042750	refactoring module manager	2019-08-23 12:52:01 -06:00
tangxifan	732e24767f	developing module manager	2019-08-22 23:49:35 -06:00
tangxifan	29104b6fa5	rework on the circuit model ports and start prototyping mux Verilog generation	2019-08-20 15:24:53 -06:00