tangxifan
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3c10af7f2b
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bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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5368485bd6
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keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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0bee70bee6
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finish memory bank configuration protocol support.
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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51e1559352
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add fabric bitstream support for memory bank configuration protocol
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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8298bbff78
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bug fixed in the fabric bitstream for frame-based configurable memories.
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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cff5b5cfc1
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break the configuration testbench. This commit is to spot which modification leads to the problem
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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85921dcc05
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add fabric bitstream builder for frame-based configuration protocol
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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4a0e1cd908
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add fabric bitstream data structure and deploy it to Verilog testbench generation
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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a26d31b87f
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make write bitstream online
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2020-02-26 11:09:23 -07:00 |
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tangxifan
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86c7c24701
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add fabric bitstream generation online
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2020-02-23 20:58:17 -07:00 |