5 Commits

Author	SHA1	Message	Date
tangxifan	c96f0d199d	[FPGA-Verilog] Adding bus group support in Verilog testbenches	2022-02-17 23:14:28 -08:00
tangxifan	4b3f906f11	[Lib] Fixed all the syntax errors	2022-02-17 17:09:03 -08:00
tangxifan	76cf4e1662	[Lib] Add reader and writer for bus group	2022-02-17 16:17:37 -08:00
tangxifan	1edaa04715	[Lib] Adding XML parser for the bus group	2022-02-17 15:50:44 -08:00
tangxifan	b44701bc2c	[Lib] Adding the 1st version of bus group data structure	2022-02-17 15:02:37 -08:00