4 Commits

Author	SHA1	Message	Date
tangxifan	185e574738	removed redundant include files in all the verilog netlists except the top one	2020-04-24 20:21:32 -06:00
tangxifan	e811f8bb21	plug in netlist manager and now the include_netlist appears in one unique file	2020-04-23 20:42:11 -06:00
tangxifan	60f40a9657	use constant module manager as much as possible in Verilog writer	2020-02-16 16:35:26 -07:00
tangxifan	cf34339e96	adapt essential gates for submodule generation	2020-02-16 11:57:19 -07:00