2 Commits

Author	SHA1	Message	Date
tangxifan	5eb04e6fff	[HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals	2020-11-22 20:53:32 -07:00
tangxifan	019208ec0f	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00