tangxifan
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8bc70b590a
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[core] developing fpga_core insertion
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2023-06-17 23:42:45 -07:00 |
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tangxifan
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50e201feeb
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[core] now clock routing for programmable clock network works for 1 clock design
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2023-03-07 13:13:25 -08:00 |
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tangxifan
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6f2572324e
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[core] developing route clock rr_graph command
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2023-02-28 11:52:38 -08:00 |
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tangxifan
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7f07a9d031
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[lib] add default seg/switch to clock arch. Fixed syntax
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2023-02-24 19:15:39 -08:00 |
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tangxifan
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786b458a27
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[core] adding new command 'append_clock_rr_graph'
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2023-02-23 13:30:18 -08:00 |
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tangxifan
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e1dab3d227
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[code] format
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2023-02-22 22:01:24 -08:00 |
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tangxifan
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e175472a07
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[core] adding new commands
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2023-02-22 21:58:25 -08:00 |
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tangxifan
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b569d6b603
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[core] format
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2023-01-07 11:40:17 -08:00 |
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tangxifan
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4385b364af
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[code] now setup command can be hidden optionally
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2023-01-07 11:18:43 -08:00 |
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tangxifan
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2fc047daff
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[core] format
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2023-01-06 21:11:12 -08:00 |
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tangxifan
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26c294679a
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[core] now setup commands follow templates
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2023-01-06 20:52:37 -08:00 |