4 Commits

Author	SHA1	Message	Date
tangxifan	13cd48c119	add support on packable/unpackable modes in VPR architecture	2020-04-06 16:07:49 -06:00
tangxifan	b09b051249	add all the test cases considering tileable, carry chain, direct connection and memory blocks	2020-03-27 13:58:35 -06:00
tangxifan	f90dc5c296	remove redundant XML codes	2020-03-12 20:44:07 -06:00
tangxifan	01c80b9126	add sample architecture to be used for Openfpga	2020-01-27 13:39:13 -07:00