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OpenFPGA
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2 Commits

Author SHA1 Message Date
tangxifan 60f40a9657 use constant module manager as much as possible in Verilog writer 2020-02-16 16:35:26 -07:00
tangxifan 99c3712b6f adapt Verilog wire module writer 2020-02-16 12:59:37 -07:00