riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
1,913 Commits 70 Branches 8 Tags 105 MiB
Commit Graph

2 Commits

Author SHA1 Message Date
tangxifan 60f40a9657 use constant module manager as much as possible in Verilog writer 2020-02-16 16:35:26 -07:00
tangxifan cf34339e96 adapt essential gates for submodule generation 2020-02-16 11:57:19 -07:00