2 Commits

Author	SHA1	Message	Date
tangxifan	60f40a9657	use constant module manager as much as possible in Verilog writer	2020-02-16 16:35:26 -07:00
tangxifan	a88c4bc954	add decode utils to libopenfpga and adapt local decoder writer in Verilog	2020-02-16 12:21:59 -07:00