4 Commits

Author	SHA1	Message	Date
tangxifan	80bb2baae5	start verification and bug fixing	2020-02-28 14:29:01 -07:00
tangxifan	65c81e14b2	add simulation ini file writer	2020-02-27 18:01:47 -07:00
tangxifan	f558405887	ported verilog testbench generator online. Split from fabric generator. Testing to be done	2020-02-27 12:33:09 -07:00
tangxifan	4cb61e2138	bring preprocessing flag Verilog netlists online	2020-02-16 00:03:24 -07:00