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OpenFPGA
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4 Commits

Author SHA1 Message Date
tangxifan 861c449606 support wired LUT in FPGA-SPICE and FPGA-Verilog 2018-11-15 15:57:49 -07:00
Baudouin Chauviere 9538dbd644 Config script written and changed some rights for some files 2018-10-24 15:59:32 -06:00
Baudouin Chauviere 31c3eba111 ReadMe modifications to add the beginning of the FPGA-SPICE tutorial 
Modifications on the addresses aswell and the different commands when they were not working.
To do still:
-create a script to change the addresses when needed
-continue the tutorial
 2018-09-27 09:33:39 -06:00
Xifan Tang fe13168f8f Add ABC and ACE2, fix bugs for fpga_flow and VPR 2018-07-27 22:54:52 -06:00