Commit Graph

6 Commits

Author SHA1 Message Date
tangxifan 3a708cff21 [Tool] Bug fix to enable nature fracturable LUT design 2020-11-25 23:01:18 -07:00
tangxifan 83e26adf90 add module usage types for future FPGA-SPICE development 2020-07-04 22:33:54 -06:00
tangxifan e089b0ef22 use constant string for inverted port naming 2020-06-11 19:31:07 -06:00
tangxifan 8ac6e10727 bug fix in lut and mux module generation on supporting spypads 2020-04-22 14:41:16 -06:00
tangxifan cf440f92d3 put routing module builder util function online 2020-02-13 16:05:23 -07:00
tangxifan e842150cc5 add lut module builder 2020-02-12 19:52:41 -07:00