tangxifan
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73386dd1a9
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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tangxifan
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0daf170e45
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refactored all the new functions to new source files, ready to delete legacy codes
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2019-12-04 15:38:42 -07:00 |
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tangxifan
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4398cffaaa
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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tangxifan
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9cf8683acd
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add module generation for memories
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2019-10-22 15:31:08 -06:00 |
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tangxifan
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81093f0db6
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add lut module generation and simplify Verilog generation codes
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2019-10-21 17:54:15 -06:00 |
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tangxifan
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6f42aac626
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add wire connection in Verilog module declaration
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2019-10-08 20:14:38 -06:00 |
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tangxifan
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1e187f3d15
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start adding memory circuit to Switch blocks
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2019-09-27 18:08:37 -06:00 |
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tangxifan
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79fa858f36
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remove unused ports for Verilog modules
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2019-09-11 19:39:59 -06:00 |
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tangxifan
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2bed51bf29
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minor bug fix for echo
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2019-09-11 17:41:45 -06:00 |
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tangxifan
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0399319212
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refactored LUT Verilog generation
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2019-09-11 17:04:43 -06:00 |