3 Commits

Author	SHA1	Message	Date
tangxifan	129caea38c	[Architecture] Patch configurable latch Verilog HDL with resetb	2020-09-23 18:30:48 -06:00
tangxifan	906191e931	[Architecture] Use strict latch Verilog HDL in frame-based procotol	2020-09-23 17:58:13 -06:00
tangxifan	b242ab79bd	[OpenFPGA Flow] Add Verilog HDL for configurable latch with active-low reset	2020-09-23 17:19:02 -06:00