Aram Kostanyan
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758453f725
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Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
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2022-01-21 02:21:00 +05:00 |
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Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
tangxifan
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824a03bdca
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[Flow] Patch new test case
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2022-01-02 20:20:36 -08:00 |
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tangxifan
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55da99f4ca
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[Flow] Add a new test case to validate DSP with registers
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2022-01-02 20:08:23 -08:00 |
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tangxifan
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6291871faf
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[Test] Added a test for the example architecture with 2x2 DSP blocks
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2021-04-26 16:28:43 -06:00 |
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tangxifan
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80f98328df
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[Test] Update test settings for architecture with fracturable DSP blocks
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2021-04-24 15:16:50 -06:00 |
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tangxifan
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1c6b9a23d7
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[Test] Add new test for multi-mode 16-bit DSP blocks
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2021-04-24 13:29:29 -06:00 |
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tangxifan
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189c94ff19
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[Test] Deploy new mac benchmarks to tests
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2021-04-23 20:44:14 -06:00 |
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tangxifan
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8c970a792a
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[Test] Add a new test case for heterogeneous FPGA using single-mode 8-bit multiplier
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2021-03-23 15:33:00 -06:00 |