tangxifan
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fedb1bd2e3
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[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp
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2022-01-25 16:41:36 -08:00 |
Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
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tangxifan
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6122863548
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[Test] Add a test case to validate the multi-shift-register-chain QL memory bank
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2021-10-09 20:44:28 -07:00 |
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tangxifan
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fa1908511d
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[Test] Added a new test case to validate QuickLogic memory using shift registers with WLR control
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2021-10-04 16:36:20 -07:00 |
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tangxifan
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dda147e234
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[Flow] Add an example simulation setting file for defining programming shift register clocks
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2021-10-01 11:04:23 -07:00 |
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tangxifan
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89a97d83bd
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[Test] Added a new test case for the shift register banks in QuickLogic memory banks
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2021-09-29 16:28:06 -07:00 |
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tangxifan
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4400dae108
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[Test] Bug fix in the wrong arch name
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2021-09-28 11:40:25 -07:00 |
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tangxifan
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dae3554fd4
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[Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals
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2021-09-28 11:27:49 -07:00 |
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tangxifan
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655b195d8b
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[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level
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2021-09-22 15:56:44 -07:00 |
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tangxifan
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51fc222d61
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[Test] Added a new test case for multi-region QL memory bank
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2021-09-22 10:01:33 -07:00 |
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tangxifan
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60fc3ab36c
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[Test] Added a new test case for the WLR memory bank
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2021-09-20 11:20:36 -07:00 |
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tangxifan
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b82cfdf555
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[Test] Add the QL memory bank test to regression test cases
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2021-09-09 09:29:21 -07:00 |
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tangxifan
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30c2f597f2
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[Test] Added two cases to validate testbench generation without self checking
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2021-06-29 16:06:15 -06:00 |
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tangxifan
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462326aaa5
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[Test] Update full testbench test case for flatten configuration protocol using 'write_full_testbench'
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2021-06-07 21:50:00 -06:00 |
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tangxifan
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5ecd975ec7
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[Test] Bug fix
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2021-06-07 19:20:10 -06:00 |
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tangxifan
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9556f994b4
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[Test] Use 'write_full_testbench' in all the memory bank -related test cases
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2021-06-07 17:49:40 -06:00 |
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tangxifan
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a67196178e
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[Test] Now use 'write_full_testbench' in configuration frame test cases
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2021-06-07 13:58:15 -06:00 |
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tangxifan
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27fa15603a
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[Tool] Patch test case due to changes in the template script
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2021-06-04 18:17:47 -06:00 |
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tangxifan
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5f96d440ec
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[Test] Deploy 'write_full_testbench' openfpga shell script to multi-headed configuration chain with auto-tuned fast configuration
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2021-06-04 11:48:05 -06:00 |
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tangxifan
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ec203d3a5c
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[Test] Deploy 'write_full_testbench' openfpga shell script to all the fast configuration chain test cases
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2021-06-04 11:35:23 -06:00 |
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tangxifan
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2068291de0
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[Test] Now deploy the 'write_full_testbench' openfpga shell script to all the configuration chain test cases
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2021-06-04 11:32:49 -06:00 |
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tangxifan
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aa4e1f5f9a
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[Test] Update test case which uses write_full_testbench openfpga shell script
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2021-06-04 11:29:43 -06:00 |
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tangxifan
|
ebe30fc070
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[Test] Deploy write full testbench to multi-head configuration chain test case
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2021-06-03 17:08:33 -06:00 |
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tangxifan
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1e9f6eb439
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[Test] update configuration chain test to use new testbench
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2021-06-03 15:53:27 -06:00 |
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tangxifan
|
f1658cb735
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[Test] Deploy blinking to test cases
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2021-05-06 15:17:45 -06:00 |
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tangxifan
|
06af30ef10
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[Test] Add test case for the SCFF usage in configuration chain
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2021-01-04 17:30:19 -07:00 |
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tangxifan
|
655da9f3d0
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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tangxifan
|
4c14428400
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[Test] Add test case for fast configuration support on multi-region frame-based configuration protocol
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2020-10-30 10:50:00 -06:00 |
|
tangxifan
|
ca7d43275d
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[Test] Add test case for multi_region configuration frame
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2020-10-30 10:48:29 -06:00 |
|
tangxifan
|
241ebf054a
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[Test] Add a test case for validating fast configuration techniques on multi-region memory banks
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2020-10-29 16:29:46 -06:00 |
|
tangxifan
|
ff386001c4
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[Test] Add openfpga task for multi-region memory banks
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2020-10-29 13:56:32 -06:00 |
|
tangxifan
|
a0d1d68402
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[Regression Test] Add regression tests for smart fast configuration chain using multiple regions
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2020-09-29 13:53:41 -06:00 |
|
tangxifan
|
5be5835b71
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[Regression Test] Add multiple region configuration chain test case
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2020-09-29 13:48:39 -06:00 |
|
tangxifan
|
19dd3778d9
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[Architecture] Add test case for memory bank to use both reset and set
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2020-09-24 17:04:24 -06:00 |
|
tangxifan
|
335f5b78c1
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[Regression Test] Add test case to use both set and reset for configuration frame
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2020-09-24 17:02:28 -06:00 |
|
tangxifan
|
2d81ff9012
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[Regression test] Add configuration chain test case where both set and reset are used
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2020-09-24 16:59:52 -06:00 |
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tangxifan
|
7fbccdd102
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[Regression Tests] Add test cases for configuration chain using different DFF cells
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2020-09-24 14:34:12 -06:00 |
|
tangxifan
|
e7906899dd
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[Regression test] Bug fix for fast configuration frame. Now should use a latch with reset
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2020-09-24 13:53:12 -06:00 |
|
tangxifan
|
ffd1a72d22
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[Architecture] Add regression tests for the frame-based configuration using reset and set signals
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2020-09-24 12:18:26 -06:00 |
|
tangxifan
|
fde15c4f88
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[Regression Test] Add test for fast memory bank configuration using set signals
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2020-09-24 12:13:35 -06:00 |
|
tangxifan
|
48083d2276
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[Regression Test] Adapt fast memory bank test case
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2020-09-24 10:32:03 -06:00 |
|
tangxifan
|
186f00edfc
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[Regression Test] Add test cases for memory bank using different SRAM cells
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2020-09-24 10:25:03 -06:00 |
|
tangxifan
|
5b0d451f0f
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[Regression Test] Add test case for configurable latch with active-low set
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2020-09-23 23:04:10 -06:00 |
|
tangxifan
|
8e780635df
|
[Regression Test] Rename test case in CI
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2020-09-23 22:59:46 -06:00 |
|
tangxifan
|
d0cef68242
|
[Regression test] Add test case for using resetb
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2020-09-23 22:58:59 -06:00 |
|
tangxifan
|
73e59d67af
|
[Architecture] Add test case for fast configuration using set signals
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2020-09-23 21:50:23 -06:00 |
|
tangxifan
|
349aa79069
|
[Regression test] Add test case for smart fast configuration
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2020-09-23 21:49:38 -06:00 |
|
tangxifan
|
05c2e652a4
|
[Regression Test] Add a new test case for using scan-chain ff in frame-based configuration protocol
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2020-09-23 20:44:06 -06:00 |
|
tangxifan
|
906191e931
|
[Architecture] Use strict latch Verilog HDL in frame-based procotol
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2020-09-23 17:58:13 -06:00 |
|
tangxifan
|
ad385c6d69
|
[Regression Test] Add test case for using SRAM cell in frame-based configuration
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2020-09-23 17:39:36 -06:00 |