4 Commits

Author	SHA1	Message	Date
tangxifan	87b2c1f3b8	[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation	2021-01-15 12:01:53 -07:00
tangxifan	81e56d45d6	[Tool] Update FPGA-SDC to use the new data structure for global ports	2020-11-10 21:17:17 -07:00
tangxifan	de8425874c	use user defined critical path delay in SDC generation	2020-02-28 11:24:39 -07:00
tangxifan	e45fa18c4c	adapt PnR SDC writer	2020-02-28 10:06:35 -07:00