tangxifan
|
7ca1a5bdc1
|
Fabric bitstream now allocates vectors in conditions for memory efficiency
|
2020-07-03 10:17:03 -06:00 |
|
tangxifan
|
9f19c36a89
|
use char in fabric bitstream to save memory footprint
|
2020-07-02 15:56:50 -06:00 |
|
tangxifan
|
b85af57971
|
optimizing fabric bitsteream memory footprint
|
2020-07-02 12:39:18 -06:00 |
|
tangxifan
|
3c10af7f2b
|
bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
5368485bd6
|
keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
0bee70bee6
|
finish memory bank configuration protocol support.
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
51e1559352
|
add fabric bitstream support for memory bank configuration protocol
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
8298bbff78
|
bug fixed in the fabric bitstream for frame-based configurable memories.
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
cff5b5cfc1
|
break the configuration testbench. This commit is to spot which modification leads to the problem
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
85921dcc05
|
add fabric bitstream builder for frame-based configuration protocol
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
4a0e1cd908
|
add fabric bitstream data structure and deploy it to Verilog testbench generation
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
a26d31b87f
|
make write bitstream online
|
2020-02-26 11:09:23 -07:00 |
|
tangxifan
|
86c7c24701
|
add fabric bitstream generation online
|
2020-02-23 20:58:17 -07:00 |