5 Commits

Author	SHA1	Message	Date
tangxifan	44d21ebb90	fixed a bug in Verilog generator supporting SRAM5T	2019-06-13 14:42:39 -06:00
tangxifan	1776ae3ec8	add explicit port mapping for inverters of memory decoders	2019-06-10 17:36:14 -06:00
tangxifan	009e5244d3	minor fix on the port direction of configuration peripherals for memory decoders	2019-06-10 15:39:35 -06:00
Baudouin Chauviere	2019840d7c	cleaned unused variables	2019-05-13 14:45:02 -06:00
tangxifan	46d44fa42a	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00