4 Commits

Author	SHA1	Message	Date
tangxifan	4bf0a63ae6	bug fixed for multiple io types defined in FPGA architectures	2020-03-27 16:32:15 -06:00
tangxifan	b6bdf78d95	bug fixed for heterogeneous block instances in top module	2020-03-24 17:39:26 -06:00
tangxifan	fc6abc13fd	add physical tile utils to identify pins that have Fc=0	2020-03-21 21:02:47 -06:00
tangxifan	9dc9c2c9f7	add build top module connection functions	2020-02-14 10:45:24 -07:00