riscv
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OpenFPGA
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326 Commits 72 Branches 8 Tags 105 MiB
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3 Commits

Author SHA1 Message Date
AurelienUoU 4f921b03da Add travis full path to avoid missing sources 2019-05-16 15:51:10 -06:00
AurelienUoU f31339bb5c Correctly instantiate script variables 2019-05-16 14:30:16 -06:00
AurelienUoU 57d75520a6 Verilog verification with Travis 2019-05-15 15:57:05 -06:00