AurelienUoU
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2b04376209
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Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks
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2019-05-22 13:44:48 -06:00 |
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AurelienUoU
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b4c97f86a3
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Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches
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2019-05-21 17:24:06 -06:00 |
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AurelienUoU
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199cd99b23
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Add dummy clock name in ace2 commands
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2019-05-21 10:35:12 -06:00 |
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AurelienUoU
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2392d11790
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Add debug command to understandn travis issue with ace
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2019-05-20 16:06:37 -06:00 |
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AurelienUoU
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becb90cd16
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Correct syntax error in ace2 log file generation
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2019-05-20 13:56:50 -06:00 |
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AurelienUoU
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82c76a2c39
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Test removing the shell specification in fpga_flow.pl
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2019-05-20 10:35:33 -06:00 |
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AurelienUoU
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43a64c26e8
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Change tcsh to csh in fpga_flow.pl -> tcsh not found by travis
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2019-05-20 09:44:38 -06:00 |
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AurelienUoU
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17ad905b14
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Update flow and allow netlist generation
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2019-05-17 17:00:38 -06:00 |
tangxifan
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4f5f8de46f
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Add Yosys and update flow_flow Perl Script
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2018-11-30 21:14:43 -07:00 |
Baudouin Chauviere
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9611576d6a
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Update on the examples to respect the new syntax
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2018-11-19 15:50:29 -07:00 |
Baudouin Chauviere
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9538dbd644
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Config script written and changed some rights for some files
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2018-10-24 15:59:32 -06:00 |
Xifan Tang
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1cf066d3ad
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Fixing minor bugs
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2018-09-06 14:25:23 -06:00 |
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Xifan Tang
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42da9160f0
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Clean codes and update
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2018-09-04 17:49:20 -06:00 |
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Xifan Tang
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00ecd0bb1d
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Cleanup codes and organization
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2018-09-04 17:31:30 -06:00 |
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Xifan Tang
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cb15bb5082
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Clean code and fix minor bugs
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2018-08-10 13:46:00 -06:00 |
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Xifan Tang
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fe13168f8f
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Add ABC and ACE2, fix bugs for fpga_flow and VPR
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2018-07-27 22:54:52 -06:00 |
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Xifan Tang
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158dec405e
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Reorganize the code directory
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2018-07-26 11:28:21 -06:00 |