AurelienUoU
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cc0bfdd548
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Add testcase in regression test for architecture with 1 IO cell/IO block
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2019-09-20 10:27:26 -06:00 |
tangxifan
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0f0d06aad7
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add non-LUT intermediate buffer to test and apply minor bug fix
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2019-09-18 15:04:51 -06:00 |
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tangxifan
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5abbfd6a0f
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add tileable routing to regression test
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2019-09-16 20:45:02 -06:00 |
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tangxifan
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d2d750a15c
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debugged rram mux branch Verilog generation
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2019-09-02 16:21:29 -06:00 |
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tangxifan
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94538b5062
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add more testing architecture
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2019-08-27 18:44:58 -06:00 |
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tangxifan
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3fb3082447
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add more tests
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2019-08-23 14:10:01 -06:00 |
Ganesh Gore
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52d6a9e979
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-08-23 13:41:29 -06:00 |
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Ganesh Gore
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28dde899db
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Updated Architecture Template
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2019-08-23 12:44:45 -06:00 |
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tangxifan
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520630c5e2
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add more testing tasks
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2019-08-23 10:16:52 -06:00 |
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Ganesh Gore
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5116aa2ae1
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Added architecture and replaced variables
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2019-08-19 19:02:50 -06:00 |
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Ganesh Gore
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66bb8a5e4b
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Updated RRAM architecture file
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2019-08-17 02:20:04 -06:00 |
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Ganesh Gore
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7bfc48b8e4
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Moved spice and verilog netlist folder location
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2019-08-17 01:49:49 -06:00 |
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Ganesh Gore
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9ab57d1b2e
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Added fpga_flow script - Working Yosys
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2019-08-09 16:49:05 -06:00 |
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Ganesh Gore
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b82369dd96
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Added first draft of fpga_task script
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2019-08-09 00:17:06 -06:00 |