tangxifan
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48b0ba8b78
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[core] format
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2023-07-24 15:00:26 -07:00 |
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tangxifan
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812473ef04
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[core] fixed the bug on io location map for tiled top module
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2023-07-24 14:50:39 -07:00 |
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tangxifan
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b70f7fb1b6
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[core] now option conflicts in command 'build_fabric' can error out
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2023-07-20 21:22:07 -07:00 |
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tangxifan
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6607bb7e48
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[core] now fpga verilog supports tile modules
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2023-07-18 22:35:22 -07:00 |
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tangxifan
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c2ef5ca408
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[core] developing top-left style tile info
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2023-07-14 22:48:44 -07:00 |
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tangxifan
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091ac88c7e
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[lib] code format
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2023-07-14 12:16:40 -07:00 |
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tangxifan
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3bc959dcec
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[lib] create tile config lib and start integration to core
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2023-07-14 12:13:31 -07:00 |
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tangxifan
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c58035dbd4
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[core] start developing option --group_tile for build_fabric
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2023-07-14 11:01:04 -07:00 |
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tangxifan
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3de4d3fc09
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[core] add a new command 'write_fabric_key' and now writer supports module-level keys
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2023-07-08 18:12:51 -07:00 |
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tangxifan
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150653287d
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[core] supporting io naming for verilog testbench generators
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2023-06-25 15:29:27 -07:00 |
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tangxifan
|
8bd9ae02fd
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[core] io name map now supports dummy port direction
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2023-06-23 11:09:33 -07:00 |
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tangxifan
|
7961223eac
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[core] enabling io naming rules in fabric builder
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2023-06-22 22:18:09 -07:00 |
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tangxifan
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c7ade72200
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[core] code complete for the core wrapper creator. Start debugging
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2023-06-18 19:17:42 -07:00 |
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tangxifan
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8bc70b590a
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[core] developing fpga_core insertion
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2023-06-17 23:42:45 -07:00 |
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tangxifan
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52e803804d
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[core] add missing file
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2023-01-06 22:37:55 -08:00 |