tangxifan
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6793c67c8d
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refactored pb_type and grid Verilog generation
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2019-10-13 21:07:30 -06:00 |
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tangxifan
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b581399761
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add memory ports and nets to intermediate pb_types
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2019-10-13 17:45:32 -06:00 |
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tangxifan
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cab4bd6807
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add gpio ports to pb_type modules
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2019-10-13 16:23:22 -06:00 |
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tangxifan
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0f50251b3b
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add mux and associated memory modules in refactoring Verilog generation for pb_types
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2019-10-13 11:11:19 -06:00 |
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tangxifan
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85644d07ae
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refactoring pb interc Verilog generation
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2019-10-12 21:55:53 -06:00 |
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tangxifan
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d1948c82eb
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Refactoring Verilog generation intermediate level of pb_types and SRAM port generation
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2019-10-11 21:43:47 -06:00 |
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tangxifan
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b3ca0d32a4
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remove configuration bus naming dependency on SRAM circuit models
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2019-10-11 19:47:36 -06:00 |
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tangxifan
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73a5977e0d
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Debugged Verilog generation for primitive pb_types
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2019-10-11 18:00:37 -06:00 |
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tangxifan
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663b1b7665
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refactorint net addition for configuration signals in module graph
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2019-10-11 13:07:14 -06:00 |
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tangxifan
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c9950162d1
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start plug in new Verilog writer. Start debugging
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2019-10-10 22:02:46 -06:00 |
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tangxifan
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9cb6e64ab3
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refactoring instanciation inside primitive pb_type Verilog module
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2019-10-08 21:29:42 -06:00 |
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tangxifan
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6bed89c237
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refactored counting config bits for circuit model and update Verilog generation for primitive pb_types
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2019-10-08 18:00:04 -06:00 |
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tangxifan
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ea2942640e
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refactored port addition for pb_types in Verilog generation
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2019-10-08 14:03:17 -06:00 |
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tangxifan
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512e9f4e8e
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refactoring Verilog generation for primitive pb_types
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2019-10-08 12:10:26 -06:00 |
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tangxifan
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173b886314
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add module name generation for pb_types
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2019-10-07 21:09:54 -06:00 |
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tangxifan
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86c9af872e
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refactoring physical block Verilog generation
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2019-10-07 17:39:00 -06:00 |
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tangxifan
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997bfdbb95
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move the refactored function for physical block Verilog generation to a new source file
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2019-10-07 16:03:15 -06:00 |