4 Commits

Author	SHA1	Message	Date
tangxifan	bba476fef4	add explicit port mapping support to Verilog testbench generator	2020-06-11 19:31:07 -06:00
tangxifan	910be3cadb	massively deploy disable_timing for configure ports in CI	2020-06-11 19:31:06 -06:00
tangxifan	1943929353	add write_fabric_hierarchy to regression tests	2020-06-11 19:31:04 -06:00
tangxifan	e78643f108	add flatten routing test case to Travis CI	2020-04-12 20:06:40 -06:00