AurelienUoU
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c76dbaac33
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Update regression test avoiding overwritting files
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2019-06-14 11:44:44 -06:00 |
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AurelienUoU
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bf13c1f731
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Add a script to create a new file with correct path rather than overwrite the existing
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2019-06-11 14:28:58 -06:00 |
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AurelienUoU
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345a081eff
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Correct error of target to rewrite file in regression test
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2019-06-07 17:37:56 -06:00 |
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AurelienUoU
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182d49da45
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Update regression test scripts
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2019-06-06 11:47:51 -06:00 |
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AurelienUoU
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a2f6ded2a2
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Add path modification in file changing a keyword into OpenFPGA full path
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2019-06-04 15:21:15 -06:00 |
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AurelienUoU
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17ad905b14
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Update flow and allow netlist generation
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2019-05-17 17:00:38 -06:00 |
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AurelienUoU
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f31339bb5c
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Correctly instantiate script variables
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2019-05-16 14:30:16 -06:00 |
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AurelienUoU
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c4ccff4562
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Move Verilog test in another script to avoid false failure
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2019-05-16 09:05:30 -06:00 |