3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
...
* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
0b82b6439b
[Regression] Upgraded runtime enviroment to python3.8
2021-01-26 16:40:45 -07:00
2b959290e9
[Test] Deploy multi-clock test to CI
2021-01-13 15:44:19 -07:00
62eb6e24cb
[Test] Add SCFF configuration chain test case to CI
2021-01-04 17:42:49 -07:00
1f994319fd
Adding this testcase to CI script. Also adding an option in ys script for synthesis to use openfpga compliant FF
2020-12-16 04:19:56 -08:00
b717903ca1
[CI] Deploy new test to CI
2020-12-04 18:51:30 -07:00
290ff028cd
[Test] Add global_tile_reset test case to CI
2020-11-30 18:12:47 -07:00
3536f0baae
[Test] Adapt regression tests scripts for github actions
2020-11-24 09:58:23 -07:00
AurelienAlacchi
Ganesh Gore
tangxifan
Lalit Sharma