10e86d334a
[test] add test cases to validate the various layouts where I/Os are in the center of the grid
2022-09-16 10:29:19 -07:00
330785635d
[test] now use a bigger fabric for the test case on custom I/O location
2022-09-13 17:53:33 -07:00
0d6e4e3979
[test] add a new example for the repack options
2022-09-12 16:21:49 -07:00
1ab7590603
[test] added a new test case to
2022-09-09 16:59:06 -07:00
d4523e819c
[test] fixed a bug
2022-09-08 16:55:50 -07:00
d76f3e3b6c
[test] fixed the bug
2022-09-08 16:34:23 -07:00
218e6d0a47
[arch] fixed syntax errors
2022-09-08 16:31:52 -07:00
a840aeea7a
[test] add a new test to validate custom I/O location syntax and deploy to basic regression tests
2022-09-08 16:27:11 -07:00
22c4d72358
[test] add a test case to validate negative edge-triggered ff
2022-05-09 16:57:42 +08:00
758453f725
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
2022-01-21 02:21:00 +05:00
6a4cc340a3
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
2022-01-17 13:21:29 +05:00
3cbe266c44
[Test] Bug fix on the test case for multi-mode FF and pin constraints
2021-07-02 15:27:27 -06:00
5286f9ba25
[Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking
2021-07-02 11:39:00 -06:00
da95da933b
[Test] Add pin constraint file to map reset to correct FPGA pins
2021-04-17 15:04:26 -06:00
7172fc9ea1
[Test] Patch test for architecture using asynchronous DFFs
2021-04-16 20:48:37 -06:00
93be81abe1
[Test] Add test case for architecture using DFF with reset
2021-04-16 20:00:48 -06:00
d12a8a03fd
[Test] Update test case using yosys bram parameters
2021-03-16 19:52:17 -06:00
73b06256d0
[Test] Deploy the new yosys script supporting BRAM to regression tests
2021-03-16 16:52:59 -06:00
3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
...
* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
655da9f3d0
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
2020-11-22 16:37:19 -07:00
3350695806
[Regression test] Add test case for pattern based local routing architecture
2020-09-23 16:06:47 -06:00
51c0319657
[Regression tests] Add test case for the k4n4 with fracturable 32-bit multiplier
2020-09-22 15:32:54 -06:00
3d1f49fb2f
[Regression Test] Add testcase for k4n4 with multiple segments
2020-09-22 12:47:41 -06:00
5741664580
[Regression Test] Add test case for k4n4 bram architecture
2020-09-22 12:23:56 -06:00
7ed9f76b06
[Regression test] Move k4n4 no local routing to basic test
2020-09-22 11:47:03 -06:00
2dea97afb6
[Regression test] reduce runtime for k4n4 test in basic testing
2020-09-22 11:45:29 -06:00
ea4dd410b7
[Regression Test] Add k4n4 fracturable lut test case to basic test
2020-09-22 11:41:36 -06:00
dad19cac9a
[Regression test] Add k4 series architecture: fracturable adder
2020-09-22 11:39:18 -06:00
tangxifan
Aram Kostanyan
AurelienAlacchi