tangxifan
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2d86a02358
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refactored LUT bitstream generation to use vtr logic
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2020-02-25 12:45:13 -07:00 |
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tangxifan
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9269d7106d
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move rr_graph back to vpr because the reader and writer requires too much dependency on the core engine
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2020-01-31 15:42:44 -07:00 |
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tangxifan
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fb0bcd7a48
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create rr_graph library to enforce unit test on the new data structures as well as compare to legacy rr_node
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2020-01-31 12:29:50 -07:00 |
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tangxifan
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f1bafffa87
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add vpr8 libs and core engine for further integration
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2020-01-03 16:14:42 -07:00 |
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tangxifan
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2c7d6e3de4
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adding port parsers
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2019-08-09 17:48:55 -06:00 |
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tangxifan
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ad8c33e1ba
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complete the mutators
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2019-08-08 11:33:11 -06:00 |
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tangxifan
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38962c4607
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adding member functions for circuit library
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2019-08-07 15:45:27 -06:00 |
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tangxifan
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44d21ebb90
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fixed a bug in Verilog generator supporting SRAM5T
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2019-06-13 14:42:39 -06:00 |