4 Commits

Author	SHA1	Message	Date
tangxifan	185e574738	removed redundant include files in all the verilog netlists except the top one	2020-04-24 20:21:32 -06:00
tangxifan	9b769cd8e4	bug fix for using renamed i/o names	2020-02-27 16:37:20 -07:00
tangxifan	f558405887	ported verilog testbench generator online. Split from fabric generator. Testing to be done	2020-02-27 12:33:09 -07:00
tangxifan	e9adb4fdbc	add preconfig top module Verilog generation	2020-02-26 20:38:01 -07:00