4 Commits

Author	SHA1	Message	Date
tangxifan	7b0c55ce15	try to reduce precision in timing assignment of Verilog netlist (travis iverilog was not happy)	2019-08-21 22:45:48 -06:00
tangxifan	9c43b1b753	complete refacotriing the inv and buf part in submodules	2019-08-21 14:54:05 -06:00
tangxifan	a40e5c91ca	refactored power-gate inverter	2019-08-20 21:56:55 -06:00
tangxifan	19472ace4e	renaming files	2019-08-20 21:01:38 -06:00