Commit Graph

10 Commits

Author SHA1 Message Date
tangxifan 0dd72999d5 deleting legacy codes: fpga_verilog top-level function 2019-12-04 15:55:16 -07:00
tangxifan 7c116aac2f added Verilog generation for preconfig top module 2019-10-29 13:54:35 -06:00
tangxifan 520e145af2 move mux_lib to fpga_x2p_setup 2019-10-19 19:13:52 -06:00
tangxifan 04f0fbebf7 plug in module graph to feed verilog writers 2019-10-18 21:59:22 -06:00
Baudouin Chauviere b48a27acf0 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-13 14:45:57 -06:00
Baudouin Chauviere 2019840d7c cleaned unused variables 2019-05-13 14:45:02 -06:00
tangxifan a3c3f2b892 developing compact routing hierarchy 2019-05-08 20:49:21 -06:00
tangxifan e305e60ee4 minor fix on the shell interface of VPR 2019-05-08 14:29:58 -06:00
tangxifan 4e3487b691 Add latest abc and update ace dependence 2019-05-03 18:56:03 -06:00
tangxifan 46d44fa42a Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00