tangxifan
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1e183e7885
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refactored shared config bits calculation
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2019-10-06 16:57:53 -06:00 |
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tangxifan
|
167778cf57
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refactoring MUX Verilog instanciation in Switch block
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2019-09-27 16:05:47 -06:00 |
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tangxifan
|
ead014e7d8
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refactoring the configuration bus Verilog generation for MUXes
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2019-09-27 11:47:34 -06:00 |
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tangxifan
|
091bbd4d9c
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start refactoring the num_config_bits for circuit model
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2019-09-26 22:53:07 -06:00 |
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tangxifan
|
f0589cc2cf
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refactoring mux Verilog generation for switch blocks
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2019-09-26 20:59:19 -06:00 |
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tangxifan
|
e0b253d30a
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minor fix for non-LUT intermedate buffer case
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2019-09-18 15:15:03 -06:00 |
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tangxifan
|
bc9d95408e
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bug fixed and refactored intermediate buffer addition
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2019-09-05 16:09:28 -06:00 |
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tangxifan
|
e623c19055
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implementing mux Verilog generation. Bugs detected, fixing ongoing
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2019-09-04 23:54:53 -06:00 |
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tangxifan
|
b6bb433edc
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bug fixing for datapath mux size in Verilog generation
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2019-09-03 18:09:21 -06:00 |
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tangxifan
|
a7ac1e4980
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remame methods in circuit_library
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2019-08-20 15:24:53 -06:00 |
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tangxifan
|
69039aa742
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developed subgraph extraction and start refactoring mux generation
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2019-08-20 15:24:53 -06:00 |
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tangxifan
|
bee070d7cc
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start plug in MUX library
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2019-08-20 15:24:53 -06:00 |
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tangxifan
|
dcca9f4f0f
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finish mux graph builders
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2019-08-20 15:24:52 -06:00 |
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tangxifan
|
638969c3c9
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adding mux graph data structures
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2019-08-20 15:24:52 -06:00 |