tangxifan
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9222d085cd
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[test] now use local clock as one of the pins in a clock bus, but connected to global routing
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2023-01-13 22:04:56 -08:00 |
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tangxifan
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5e23be19a5
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[test] now the test case that generates golden netlist use a special openfpga arch file which contains no soft paths
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2022-09-20 18:07:31 -07:00 |
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tangxifan
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812af4f722
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[arch] add arch that supports negative edge triggered flip-flop
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2022-05-09 16:32:01 +08:00 |
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tangxifan
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c8da85cc24
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[Doc] Update naming convention for OpenFPGA architecture files
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2022-03-20 10:51:55 +08:00 |
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tangxifan
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7598455497
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[Doc] Update naming convention for architecture files
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2022-01-02 19:51:09 -08:00 |
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tangxifan
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64294ae4eb
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[Doc] Update README for architecture files due to new architecture features
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2021-04-16 19:25:54 -06:00 |
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tangxifan
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2f1aceda67
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[Doc] Update documentation about architecture naming rules
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2021-01-12 18:01:24 -07:00 |
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tangxifan
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f21d22f691
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[Doc] Update README for new architectures
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2021-01-10 10:54:59 -07:00 |
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tangxifan
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17070c6405
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[Doc] Update README in openfpga arch directory for native fracturable LUT design
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2020-11-25 22:19:20 -07:00 |
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tangxifan
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fefcd88f14
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update openfpga architecture README for power-gating
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2020-07-22 21:55:59 -06:00 |
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tangxifan
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73e75bf456
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add readme for OpenFPGA architecture naming
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2020-07-01 10:27:21 -06:00 |