104 Commits

Author	SHA1	Message	Date
tangxifan	a9df922412	finish the identification on mirror switch and connection blocks ... Verilog generator to be updated	2019-05-09 21:31:39 -06:00
tangxifan	a3c3f2b892	developing compact routing hierarchy	2019-05-08 20:49:21 -06:00
tangxifan	42daadee2f	critical bug fixing	2019-04-30 14:30:17 -06:00
tangxifan	46d44fa42a	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00