5 Commits

Author	SHA1	Message	Date
Ganesh Gore	5116aa2ae1	Added architecture and replaced variables	2019-08-19 19:02:50 -06:00
Ganesh Gore	66bb8a5e4b	Updated RRAM architecture file	2019-08-17 02:20:04 -06:00
Ganesh Gore	7bfc48b8e4	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
Ganesh Gore	9ab57d1b2e	Added fpga_flow script - Working Yosys	2019-08-09 16:49:05 -06:00
Ganesh Gore	b82369dd96	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00