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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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3 Commits
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tangxifan
3077efa74f
add option to compact tileable routing arch
2019-07-04 17:13:34 -06:00
tangxifan
95674c4687
added Switch Block SubType and SubFs for tileable rr_graph generation
2019-07-02 10:00:02 -06:00
tangxifan
d683134b12
rename customized vpr7 to vpr7 XML to Production
2018-09-17 23:10:45 -06:00