5 Commits

Author	SHA1	Message	Date
tangxifan	23643f3fb1	[core] developing the physical memory block builder	2023-07-31 22:57:26 -07:00
tangxifan	6607bb7e48	[core] now fpga verilog supports tile modules	2023-07-18 22:35:22 -07:00
tangxifan	c7ade72200	[core] code complete for the core wrapper creator. Start debugging	2023-06-18 19:17:42 -07:00
tangxifan	6d31b319a2	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
tangxifan	e909f4fabe	[lib] rename libopenfpga to libs	2022-08-18 10:27:20 -07:00