tangxifan
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96f36a96dd
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[core] syntax
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2023-09-25 16:50:30 -07:00 |
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tangxifan
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0a94763422
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[lib] add module rename assistant
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2023-09-22 18:16:01 -07:00 |
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tangxifan
|
72a3c05747
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[core] code format
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2023-09-17 13:29:30 -07:00 |
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tangxifan
|
ccd4c1861b
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[core] developing new command to write module naming rules
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2023-09-16 19:37:06 -07:00 |
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tangxifan
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b5cf08a3c5
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[lib] add testing
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2023-09-15 17:15:05 -07:00 |
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tangxifan
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af67b02cca
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[lib] rename lib to namemanager as a unified library to provide naming support on FPGA modules
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2023-09-15 13:51:14 -07:00 |