Commit Graph

14 Commits

Author SHA1 Message Date
tangxifan 804b721a19 [Tool] Bug fix in the configuration chain connection builder 2021-01-04 17:41:29 -07:00
tangxifan bfd305b5a5 [Tool] Patch the bug in finding data output ports for CCFF 2021-01-04 17:22:30 -07:00
tangxifan cc91a0aebd [Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder 2021-01-04 17:14:26 -07:00
tangxifan 9adeb550dc [OpenFPGA Tool] Bug fix in fabric builder 2020-09-23 18:28:00 -06:00
tangxifan 83e26adf90 add module usage types for future FPGA-SPICE development 2020-07-04 22:33:54 -06:00
tangxifan 0bee70bee6 finish memory bank configuration protocol support. 2020-06-11 19:31:13 -06:00
tangxifan 8ec8ac4118 bug fixed in flatten memory organization. Passed verification 2020-06-11 19:31:12 -06:00
tangxifan d2d443a988 start developing memory bank and standalone configuration protocol 2020-06-11 19:31:12 -06:00
tangxifan 8298bbff78 bug fixed in the fabric bitstream for frame-based configurable memories. 2020-06-11 19:31:10 -06:00
tangxifan 65df309419 bug fixing for frame-based configuration protocol and rename some naming function to be generic 2020-06-11 19:31:10 -06:00
tangxifan 290dd1a8a6 add frame decoder builder to all the module graph builder except the top-level 2020-06-11 19:31:09 -06:00
tangxifan 8864920460 add frame-based memory module builder 2020-06-11 19:31:09 -06:00
tangxifan cf440f92d3 put routing module builder util function online 2020-02-13 16:05:23 -07:00
tangxifan 002c2795fe add memory module builder 2020-02-12 20:06:38 -07:00