tangxifan
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9832722056
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[test] now add QuickLogic memory bank to fpga bitstream regression tests
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2022-05-25 11:42:32 +08:00 |
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tangxifan
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86347a9d49
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[test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols
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2022-05-25 11:19:49 +08:00 |
Aram Kostanyan
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758453f725
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Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
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2022-01-21 02:21:00 +05:00 |
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Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
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tangxifan
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335347a74f
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[Test] Bug fix
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2021-10-30 15:48:25 -07:00 |
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tangxifan
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be47e78289
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[Arch] Change arch for Sapone test
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2021-10-30 15:23:19 -07:00 |
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tangxifan
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ad5cce0ae8
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[Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals
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2021-10-30 15:11:07 -07:00 |
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tangxifan
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16de60e943
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[Test] Turn off ACE2 run in bitstream generation only flows
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2021-10-30 12:31:14 -07:00 |
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tangxifan
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655da9f3d0
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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tangxifan
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f33422d4d7
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add regression test to track runtime on big fpga devices using practical benchmarks
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2020-07-28 12:38:42 -06:00 |
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tangxifan
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4174fbf77d
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add load architecture bitstream test case and reorganize regression tests in category of openfpga tools
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2020-07-27 15:54:46 -06:00 |