3 Commits

Author	SHA1	Message	Date
tangxifan	dfe1db996a	[Tool] Remove the hardcoded factor when computing simulation timing; There should be no hidden parameters impacting simulation time	2021-06-29 09:56:04 -06:00
tangxifan	4aa6264b1c	[Tool] Rework simulation time period to be sync with actual stimuli	2020-12-02 22:58:13 -07:00
tangxifan	bb671acac3	add formal random Verilog testbench generation	2020-02-26 20:58:16 -07:00